Driven by increasing demands for ultra-large-scale integration and high performance of integrated circuits, semiconductor technology has been scaled down the 45 nm and even smaller technology node. The success of high-k metal-gate (HKMG) in the 45 nm technology node has made it key to the process flow for the sub-30 nm technology node. Intel, who has committed to a metal-gate-last approach, is the leader and only one manufacturer in mass production of 45 nm and 32 nm chips. And former IBM alliances such as Sumsung, TSMC and Infineon have recently switched the process development route from gate-first to gate-last.
The gate-last approach presents a challenge in developing the chemical and mechanical planarization (CMP) process. A gate-last process includes, generally, removing the silicon dioxide insulating layer and the silicon nitride insulating layer on top of the poly silicon (poly) gate by CMP such that the top of the poly gate is exposed, also known as, poly opening nitride polish (POP) CMP; then, removing the poly gate, filling the resulting trench with metal layers, and performing chemical-mechanical planarization of the metal layers in one or more steps, i.e., metal-gate CMP, such that only the metal within the trench is left, thereby obtaining the HKMG structure.
FIG. 1 and FIG. 2 illustrate a conventional POP CMP process, and FIG. 3 and FIG. 4 illustrates a conventional metal gate CMP process. As shown in FIG. 1 and FIG. 2, a poly gate 11 is formed on a substrate 10, and overlay by a silicon nitride insulating layer 12 and then a silicon dioxide insulating layer 13. The POP CMP includes: firstly, CMP of the silicon dioxide insulating layer 13, exposing the silicon nitride insulating layer on top of the poly gate 11; and secondly, CMP of the silicon nitride insulating layer 12, exposing the poly gate 11. High within-die uniformity is required for both of the CMP processes, especially the CMP of the silicon dioxide insulating layer.
However, due to high poly gate density, and height differences between gates before silicon dioxide insulating layer deposition, approximately 1000 Å to 1800 Å, the thickness variation h of the silicon dioxide insulating layer 13 on top of the poly gate 11 and on the source/drain area (not shown) after silicon dioxide insulating layer deposition can be 1000 Å to 4000 Å, or even more. Conventional silicon dioxide CMP processes can not resolve a thickness variation as large as this, and it will be passed down when silicon dioxide insulating layer 13 CMP goes. As shown in FIG. 2, the variation results in a dishing 14 on the remaining silicon dioxide insulating layer 13 between poly gates 11, which can not be covered by the following CMP of the silicon nitride insulating layer 12, and may even be enlarged due to CMP process, such as slurry selectivity. As shown in FIG. 3 and FIG. 4, the dishing 14 on the silicon dioxide insulating layer will be filled with metal in a subsequent metal-gate deposition process, drastically limiting the tuning range of metal-gate CMP process, resulting in metal residue between gates and causing a short circuit in the device.